? 2003 fairchild semiconductor corporation ds011612 www.fairchildsemi.com october 1993 revised september 2003 74lvx374 low voltage octal d-type flip-flop with 3-state outputs 74lvx374 low voltage octal d-type flip-flop with 3-state outputs general description the lvx374 is a high-speed, low-power octal d-type flip- flop featuring separate d-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. a buffered clock (cp) and output enable (oe ) are common to all flip- flops. the inputs tolerate up to 7v allowing interface of 5v systems to 3v systems. features input voltage translation from 5v to 3v ideal for low power/low noise 3.3v applications guaranteed simultaneous switching noise level and dynamic threshold performance ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic symbols ieee/iec connection diagram pin descriptions order number package number package description 74lvx374m m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvx374sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lvx374mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description d 0 ? d 7 data inputs cp clock pulse input oe 3-state output enable input o 0 ? o 7 3-state outputs
www.fairchildsemi.com 2 74lvx374 truth table h = high voltage level l = low voltage level x = immaterial z = high impedance = low-to-high transition functional description the lvx374 consists of eight edge-triggered flip-flops with individual d-type inputs and 3-state true outputs. the buffered clock and buffered output enable are common to all flip-flops. the eight flip-flops will store the state of their individual d inputs that meet the setup and hold time requirements on the low-to-high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip-flops are available at the outputs. when the oe is high, the outputs go to the high impedance state. opera- tion of the oe input does not affect the state of the flip- flops. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs outputs d n cp oe o n h lh l ll xxh z
3 www.fairchildsemi.com 74lvx374 absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: unused inputs must be held high or low. they may not float. dc electrical characteristics noise characteristics (note 3) note 3: input t r = t f = 3 ns supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma dc input voltage (v i ) ? 0.5v to 7v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 25 ma dc v cc or ground current (i cc or i gnd ) 75 ma storage temperature (t stg ) ? 65 c to + 150 c power dissipation 180mw supply voltage (v cc ) 2.0v to 3.6v input voltage (v i ) 0v to 5.5v output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c input rise and fall time ( ? t/ ? v) 0 ns/v to 100 ns/v symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions min typ max min max v ih high level 2.0 1.5 1.5 input voltage 3.0 2.0 2.0 v 3.6 2.4 2.4 v il low level 2.0 0.5 0.5 input voltage 3.0 0.8 0.8 v 3.6 0.8 0.8 v oh high level 2.0 1.9 2.0 1.9 v in = v ih i oh = ? 50 a output voltage 3.0 2.9 3.0 2.9 v or v il i oh = ? 50 a 3.0 2.58 2.48 i oh = ? 4ma v ol low level 2.0 0.0 0.1 0.1 v in = v ih i ol = 50 a output voltage 3.0 0.0 0.1 0.1 v or v il i ol = 50 a 3.0 0.36 0.44 i ol = 4ma i oz 3-state output 3.6 0.25 2.5 v in = v ih or v il off-state current av out = v cc or gnd i in input leakage current 3.6 0.1 1.0 av in = 5.5v or gnd i cc quiescent supply current 3.6 4.0 40.0 av in = v cc or gnd symbol parameter v cc t a = 25 c units c l (pf) (v) typ limit v olp quiet output maximum dynamic v ol 3.3 0.5 0.8 v 50 v olv quiet output minimum dynamic v ol 3.3 ? 0.5 ? 0.8 v 50 v ihd minimum high level dynamic input voltage 3.3 2.0 v 50 v ild maximum low level dynamic input voltage 3.3 0.8 v 50
www.fairchildsemi.com 4 74lvx374 ac electrical characteristics note 4: parameter guaranteed by design. t oslh = |t plhm ? t plhn |, t oshl = |t phlm ? t phln | capacitance note 5: c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) min typ max min max f max maximum clock 2.7 60 115 50 mhz c l = 15 pf frequency 45 60 40 c l = 50 pf 3.3 0.3 100 160 85 c l = 15 pf 60 95 55 c l = 50 pf t plh propagation delay time 2.7 8.5 16.3 1.0 19.5 ns c l = 15 pf t phl cp to o n 11.0 19.8 1.0 23.0 c l = 50 pf 3.3 0.3 6.7 10.6 1.0 12.5 c l = 15 pf 9.214.11.016.0 c l = 50 pf t pzl 3-state output 2.7 7.6 14.5 1.0 17.5 ns c l = 15 pf, r l = 1 k ? t pzh enable time 10.1 18.0 1.0 21.0 c l = 50 pf, r l = 1 k ? 3.3 0.3 5.9 9.3 1.0 11.0 c l = 15 pf, r l = 1 k ? 8.412.81.014.5 c l = 50 pf, r l = 1 k ? t plz 3-state output 2.7 11.5 18.5 1.0 22.0 ns c l = 50 pf, r l = 1 k ? t phz disable time 3.3 0.3 9.6 13.2 1.0 15.0 c l = 50 pf, r l = 1 k ? t w cp pulse 2.7 7.5 8.0 ns width 3.3 0.3 5.0 5.5 t s setup time 2.7 6.5 6.5 ns d n to cp 3.3 0.3 4.5 4.5 t h hold time 2.7 2.0 2.0 ns d n to cp 3.3 0.3 2.0 2.0 t oslh output to output 2.7 1.5 1.5 ns c l = 50 pf t oshl skew (note 4) 3.3 1.5 1.5 symbol parameter t a = + 25 ct a = ? 40 c to + 85 c units min typ max min max c in input capacitance 4 10 10 pf c out output capacitance 6 pf c pd power dissipation 32 pf capacitance (note 5)
5 www.fairchildsemi.com 74lvx374 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 6 74lvx374 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
7 www.fairchildsemi.com 74lvx374 low voltage octal d-type flip-flop with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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